1. Field of the Invention
The present invention relates to an information processing apparatus and an information processing method for direct memory access (DMA) transferring information between a storage section in an information transfer system, such as a network card, and a storage section in an information processing system having a microprocessor (CPU), a program for executing the information processing method, a storage medium storing the program, a DMA controller, a DMA transfer method, a program for executing the DMA transfer method, and a storage medium storing the program. Specifically, descriptor information concerning the DMA transferred information is DMA transferred from a second storage section in the information transfer system to a first storage section in the information processing system, and the DMA transferred descriptor information is loaded from the first storage section. Thus, the descriptor information can be loaded without the need to access the second storage section in the information transfer system, which would require a long processing time, and a processing speed of the apparatus can be increased.
2. Description of the Related Art
In recent years, DMA transfer has been widely employed in order to allow information to be transferred between the storage section in the information processing system and the storage section in the information transfer system at a high speed. For example, a descriptor is stored beforehand in a register of a DMA controller in the information transfer system, e.g., the network card, and the CPU writes, to the register of the DMA controller, an address of a destination (or a source) and an amount of data to be transferred. Thereafter, the CPU issues a start command to the DMA controller, thereby initiating a DMA transfer. When the transfer of that amount of data, which has been written to the register, is complete, this transfer operation is completed. Thus, operation information such as the destination address and so on needs to be written to the register each time a transfer operation is performed, and this burdens the CPU.
By way of addressing this problem, the CPU may generate, on a random access memory (RAM), a descriptor (a DMA transfer information queue) indicating the destination address and so on, and instruct the DMA controller to start the DMA transfer. Upon receipt of the instruction to start the DMA transfer from the CPU, the DMA controller performs the DMA transfer while referring to the descriptor generated on the RAM. Thus, the CPU is capable of issuing an instruction to start data transfer asynchronously to the DMA transfer. This enables high-speed processing, in particular when a plurality of pieces of data are DMA transferred.
When the DMA transfer is complete, the DMA controller provides an interrupt to the CPU. Upon receipt of the interrupt, the CPU loads the descriptor from the register of the DMA controller. After loading the descriptor, the CPU performs a process of releasing a buffer and so on in the case where the DMA transfer completed is sequential transmission, and processes received data in the case where the DMA transfer is data reception.
In connection with the above related-art technique, Japanese Patent Laid-open No. 2002-140286 (page 6, FIGS. 3 and 5) discloses an information processing apparatus having a DMA transfer capability. In this information processing apparatus, a DMA controller 41 loads descriptor information 53 stored in an image memory 43 into a register prepared in the DMA controller 41. As a result, the DMA controller 41 is able to perform a DMA transfer process while referring to the loaded descriptor information 53.